たーぼ のハードウェア設計記録

package distance_pkg is

    -- 距離タイプ
    type distance is range 0 to integer'high
        units
            munit;

            um      = 10 munit;
            mm      = 1000 um;
            cm      = 10 mm;
            m       = 100 cm;
            km      = 1000 m;

            mil     = 254 munit;
            inch    = 1000 mil;
            ft      = 12 inch;
            yd      = 3 ft;
            fm      = 6 ft;
            mi      = 5280 ft;
            lg      = 3 mi;
        end units;

    -- 距離から遅延時間を算出
    function distance2time( trace_len : distance ) return time;

end distance_pkg;

package body distance_pkg is

    -- 距離から遅延時間を算出
    function distance2time( trace_len : distance ) return time is
        variable    resolution      : real;
        variable    delay_time      : time;
    begin
        -- シミュレーションレゾリューションの取得
        resolution := get_resolution;

        -- メートル−時間変換
        --1ns=15cm(150000um)
        --1000000fs=150000um
        --1fs=0.15um(1.5munit)
        delay_time := to_time( real( distance'pos(trace_len))
                                 /(1.5 * resolution * 1000000000000000.0));

        return delay_time;
    end;

end distance_pkg;

entity TEST is
end TEST;

architecture BEHAVIOR of TEST is

    component LINEDELAY
        generic
        (
            linedelay       : time
        );
        port
        (
            PORTA           : inout std_logic;
            PORTB           : inout std_logic
        );
    end component;

    signal  PORTA   : std_logic;
    signal  PORTB   : std_logic;
    signal  PORTA_S : std_logic;
    signal  PORTB_S : std_logic;

begin

    C_LINEDELAY : LINEDELAY
    generic map
    (
        linedelay       => 10 ns
    )
    port map
    (
        PORTA           => PORTA_S,
        PORTB           => PORTB_S
    );

    process begin
        PORTA <= 'Z';
        PORTB <= 'Z';
        wait for 100 ns;
        PORTA <= '1';
        wait for 100 ns;
        PORTA <= '0';
        wait for 100 ns;
        PORTA <= 'Z';
        PORTB <= '1';
        wait for 100 ns;
        PORTB <= '0';
        wait for 100 ns;
        PORTB <= 'Z';
        wait for 100 ns;
        PORTA <= '1';
        PORTB <= '0';
        wait for 100 ns;
        PORTA <= '0';
        PORTB <= '1';
        wait for 100 ns;
        PORTA <= '1';
        wait for 100 ns;
        PORTA <= '0';
        PORTB <= '0';
        wait for 100 ns;
    end process;

    PORTA_S <= PORTA;
    PORTB_S <= PORTB;

end BEHAVIOR;

entity LINEDELAY is
    generic
    (
        linedelay       : time
    );
    port
    (
        PORTA           : inout std_logic;
        PORTB           : inout std_logic
    );
end LINEDELAY;

architecture BEHAVIOR of LINEDELAY is

    signal  PORTA_X     : std_logic;
    signal  PORTB_X     : std_logic;

begin

    PROCESS
        VARIABLE last_time : time;
        VARIABLE transact : boolean;
    BEGIN
            WAIT ON PORTA'TRANSACTION, PORTB_X UNTIL (last_time /= NOW or PORTB_X'EVENT);

            if ( PORTA'TRANSACTION'EVENT ) then
                PORTA <= 'Z';
                transact := TRUE;
                last_time := NOW;
            else
                transact := FALSE;
            end if;

            WAIT FOR 0 ns;

            if ( transact = TRUE ) then
                PORTA_X <= transport PORTA after linedelay;
            end if;
            PORTA <= PORTB_X;

    END PROCESS;

    PROCESS
        VARIABLE last_time : time;
        VARIABLE transact : boolean;
    BEGIN
            WAIT ON PORTB'TRANSACTION, PORTA_X UNTIL (last_time /= NOW or PORTA_X'EVENT);

            if ( PORTB'TRANSACTION'EVENT ) then
                PORTB <= 'Z';
                last_time := NOW;
                transact := TRUE;
            else
                transact := FALSE;
            end if;

            WAIT FOR 0 ns;

            if ( transact = TRUE ) then
                PORTB_X <= transport PORTB after linedelay;
            end if;
            PORTB <= PORTA_X;

    END PROCESS;

end BEHAVIOR;

entity COUNT is
    port
    (
        CLK     : in    std_logic;
        COUNT   : out   std_logic_vector(7 downto 0) := (others => '0')
    );
end COUNT;

architecture rtl of COUNT is

begin

    process ( CLK ) begin
        if ( CLK'event and CLK = '1' ) then
            COUNT <= COUNT'DRIVING_VALUE + '1';        -- 内部参照
        end if;
    end process;

end rtl;

library IEEE;
use IEEE.std_logic_1164.all;

library work;
use work.shared_pkg.all;

entity a is
    port
    (
        CLK             : in    std_logic;
        DATA           : out   integer
    );
end a;

architecture a of a is
    component b
        port
        (
            CLK             : in    std_logic
        );
    end component;
begin
    u_b : b port map( CLK );
    process ( CLK ) begin
        if ( CLK'event and CLK = '1' ) then
            DATA <= SH_INT;
        end if;
    end process;
end a;

library IEEE;
use IEEE.std_logic_1164.all;

library work;
use work.shared_pkg.all;

entity b is
    port
    (
        CLK             : in    std_logic
    );
end b;

architecture b of b is
begin
    process ( CLK ) begin
        if ( CLK'event and CLK = '1' ) then
            SH_INT := SH_INT + 1;
        end if;
    end process;
end b;

    -- 共有変数をプロテクトタイプで宣言
    shared variable SH_INT      : SH_TEST;

end shared_pkg;

package body shared_pkg is

    type SH_TEST is protected body
        -- 実データ
        variable buf : integer := 0;
        -- 書き込み関数
        procedure write ( data : in integer ) is
        begin
            buf := data;
        end;
        -- 読み出し関数
        impure function read return integer is
        begin
            return buf;
        end;
    end protected body SH_TEST;

end shared_pkg;

library IEEE;
use IEEE.std_logic_1164.all;

library work;
use work.shared_pkg.all;

entity a is
    port
    (
        CLK             : in    std_logic;
        DATA            : out   integer
    );
end a;

architecture a of a is
    component b
        port
        (
            CLK             : in    std_logic
        );
    end component;
begin
    process ( CLK ) begin
        if ( CLK'event and CLK = '1' ) then
            DATA <= SH_INT.read;
        end if;
    end process;
    u_b : b port map( CLK );
end a;

library IEEE;
use IEEE.std_logic_1164.all;

library work;
use work.shared_pkg.all;

entity b is
    port
    (
        CLK             : in    std_logic
    );
end b;

architecture b of b is
begin
    process ( CLK ) begin
        if ( CLK'event and CLK = '1' ) then
            SH_INT.write( SH_INT.read + 1 );
        end if;
    end process;
end b;

-- ＦＰＧＡのトップファイルにこのパッケージを宣言する。
library work;
use work.ver_get.all;

entity top is
    generic
    (
        -- シミュレーションを行う場合は、
        -- テストベンチから「SIM_MODE」を1にして呼び出す。
        -- 合成の時はディフォルトの0が自動的に割り当たる。
        SIM_MODE            : integer := 0
    );
    port
    (
        VER_OUT         : out   std_logic_vector(31 downto 0)
    );
end top;

architecture top of top is

    -- この呼び出しで論理合成する毎にインクリメントされた値を返す。
    constant    VERSION : std_logic_vector(31 downto 0)
                                := get_version( SIM_MODE, "ver.txt" );

begin

    VER_OUT <= VERSION;

end top;

entity PP_TEST is
end PP_TEST;

architecture behavior  of PP_TEST is

    signal  CLK     : std_logic;
    signal  COUNT   : std_logic_vector(3 downto 0) := (others => '0');

begin

    -- クロック生成
    process begin
        CLK <= '0';
        wait for 10 ns;
        CLK <= '1';
        wait for 10 ns;
    end process;

    -- CLKでCOUNTをインクリメント
    process ( CLK ) begin
        if ( CLK'event and CLK = '1' ) then
            COUNT <= COUNT + '1';
        end if;
    end process;

    -- COUNTのセットアップチェック
    process ( CLK ) begin
        if ( CLK = '1' ) then
            assert ( COUNT'last_event >= 5 ns )
                report "Setup Time was not suitable."
                severity WARNING;
        end if;
    end process;

    -- COUNTのセットアップチェック
    postponed process ( CLK ) begin
        if ( CLK = '1' ) then
            assert ( COUNT'last_event >= 5 ns )
                report "Setup Time was not suitable.(postponed)"
                severity WARNING;
        end if;
    end process;

end behavior;

-- integerデータタイプの遅延モジュール
entity INT_DLY is
    generic
    (
        -- 遅延クロック数
        COUNT   : in    integer range 1 to 10 := 5;
        -- データの最大値
        DMAX    : in    integer := 128
    );
    port
    (
        CLK     : in    std_logic;
        DIN     : in    integer range 0 to DMAX;
        DOUT    : out   integer range 0 to DMAX
    );
end INT_DLY;

architecture behavior of INT_DLY is

    -- integerの配列定義
    type int_vector is array ( natural range <> ) of integer;

    -- 遅延をシフトレジスタで実現するためのレジスタ配列
    signal  DELAY   : int_vector(COUNT-1 downto 0);

begin

    -- integerのシフトレジスタ
    process ( CLK ) begin
        if ( CLK'event and CLK = '1' ) then
            DELAY(0) <= DIN;
            for i in 1 to COUNT-1 loop
                DELAY(i) <= DELAY(i-1);
            end loop;
        end if;
    end process;
    DOUT <= DELAY(COUNT-1);

end behavior;

entity test is
end test;

architecture behavior of test is

    signal  result_match    : boolean := FALSE;
    signal  result_equ      : boolean := FALSE;
    signal  testdata        : std_logic_vector(2 downto 0) := (others => '0');

begin

    -- 固定値
    testdata(2) <= '1';
    testdata(0) <= '0';

    -- std_logicの全ての状態を繰り返す
    process begin
        testdata(1)  <= 'U';
        wait for 10 ns;
        testdata(1) <= 'X';
        wait for 10 ns;
        testdata(1) <= '0';
        wait for 10 ns;
        testdata(1) <= '1';
        wait for 10 ns;
        testdata(1) <= 'Z';
        wait for 10 ns;
        testdata(1) <= 'W';
        wait for 10 ns;
        testdata(1) <= 'L';
        wait for 10 ns;
        testdata(1) <= 'H';
        wait for 10 ns;
        testdata(1) <= '-';
        wait for 10 ns;
    end process;

    -- イコール（=）で比較した場合
    process begin
        if ( testdata = "1-0" ) then
            result_equ <= TRUE;
        else
            result_equ <= FALSE;
        end if;
        wait on testdata;
    end process;

    -- std_matchを使った場合
    process begin
        if ( std_match(testdata, "1-0")) then
            result_match <= TRUE;
        else
            result_match <= FALSE;
        end if;
        wait on testdata;
    end process;

end behavior;

entity test is
end test;

architecture behavior of test is

    signal  DATA1       : std_logic := '1';
    signal  DATA2       : std_logic := '1';
    signal  DATA3       : std_logic := '1';
    signal  DATA1_TR    : integer := 0;
    signal  DATA1_EV    : integer := 0;
    signal  DATA2_TR    : integer := 0;
    signal  DATA2_EV    : integer := 0;
    signal  DATA3_TR    : integer := 0;
    signal  DATA3_EV    : integer := 0;

begin

    process begin
        wait for 5 ns;
        DATA1 <= '1' after 1 ns;
        wait for 5 ns;
        DATA1 <= '1' after 2 ns;
        wait for 5 ns;
        DATA1 <= '1' after 1 ns;
        wait for 5 ns;
        DATA1 <= '1' after 2 ns;
    end process;

    process begin
        wait for 5 ns;
        DATA2 <= '0' after 1 ns;
        wait for 5 ns;
        DATA2 <= '1' after 2 ns;
        wait for 5 ns;
        DATA2 <= '0' after 2 ns;
        wait for 5 ns;
        DATA2 <= '1' after 1 ns;
    end process;

    DATA3 <= DATA1 or DATA2;

    -- トランザクション発生でカウントアップ
    process begin
        wait on DATA1'transaction;
        DATA1_TR <= DATA1_TR + 1;
    end process;
    process begin
        wait on DATA2'transaction;
        DATA2_TR <= DATA2_TR + 1;
    end process;
    process begin
        wait on DATA3'transaction;
        DATA3_TR <= DATA3_TR + 1;
    end process;

    -- イベント発生でカウントアップ
    process begin
        wait on DATA1;
        DATA1_EV <= DATA1_EV + 1;
    end process;
    process begin
        wait on DATA2;
        DATA2_EV <= DATA2_EV + 1;
    end process;
    process begin
        wait on DATA3;
        DATA3_EV <= DATA3_EV + 1;
    end process;

end behavior;

package body test_pkg is
    -- ディファード定数の定数決定
    constant    const_int   : integer := 10;
end test_pkg;

entity PASSIVE_TEST is
    generic
    (
        SETUP   : in    time := 10 ns;
        HOLD    : in    time := 5 ns
    );
    port
    (
        CLK     : in    std_logic;
        DIN     : in    std_logic;
        DOUT    : out   std_logic
    );

begin
-- XSTはパッシブプロセスをサポートしていない
-- pragma translate_off
    process
        variable    PREV_DIN        : std_logic := 'U';
        variable    PREV_DIN_TIME   : time      := 0 ns;
        variable    PREV_CLK_TIME   : time      := 0 ns;
    begin
        -- CLKかDINに変化があれば次に進む
        wait on     CLK, DIN;

        -- DINに変化があった場合
        if ( DIN /= PREV_DIN ) then
            PREV_DIN_TIME   := now;
            PREV_DIN        := DIN;
            if ( now - PREV_CLK_TIME < HOLD ) then
                assert false
                report "Hold Time was not suitable."
                severity WARNING;
            end if;
        end if;

        -- CLKに変化があった場合
        if ( CLK'event and CLK = '1' ) then
            PREV_CLK_TIME   := now;
            if ( now - PREV_DIN_TIME < SETUP ) then
                assert false
                report "Setup Time was not suitable."
                severity WARNING;
            end if;
        end if;

    end process;
-- pragma translate_on
end PASSIVE_TEST;

-- ビヘイビア１
architecture BEHAVIOR1 of PASSIVE_TEST is
begin

    process ( CLK ) begin
        if ( CLK'event and CLK = '1' ) then
            DOUT <= DIN;
        end if;
    end process;

end BEHAVIOR1;

-- ビヘイビア２
architecture BEHAVIOR2 of PASSIVE_TEST is
begin

    process ( CLK ) begin
        if ( CLK'event and CLK = '1' ) then
            DOUT <= DIN after 2 ns;
        end if;
    end process;

end BEHAVIOR2;

entity PASSIVE_TEST_TB is
end PASSIVE_TEST_TB;

architecture behavior of PASSIVE_TEST_TB is

    component PASSIVE_TEST
        generic
        (
            SETUP   : in    time := 10 ns;
            HOLD    : in    time := 5 ns
        );
        port
        (
            CLK     : in    std_logic;
            DIN     : in    std_logic;
            DOUT    : out   std_logic
        );
    end component;

    signal  CLK     : std_logic := '1';
    signal  DIN     : std_logic := '0';
    signal  DOUT    : std_logic := '0';

begin

    U_PASSIVE_TEST : PASSIVE_TEST
    generic map
    (
        SETUP   => 10 ns,
        HOLD    => 5 ns
    )
    port map
    (
        CLK     => CLK,
        DIN     => DIN,
        DOUT    => DOUT
    );

    process begin
        CLK <= '1';
        wait for 50 ns;
        CLK <= '0';
        wait for 50 ns;
    end process;

    process begin
        DIN <= '0' after 3 ns;      -- Hold Error;
        wait for 200 ns;
        DIN <= '1' after 91 ns;     -- Setup Error;
        wait for 200 ns;
    end process;

end behavior;

-- ビヘイビア１を選択
configuration PASSIVE_TEST_CONFIG1 of PASSIVE_TEST_TB is
    for behavior
        for U_PASSIVE_TEST : PASSIVE_TEST use entity work.passive_test(BEHAVIOR1);
        end for;
    end for;
end PASSIVE_TEST_CONFIG1;

-- ビヘイビア２を選択
configuration PASSIVE_TEST_CONFIG2 of PASSIVE_TEST_TB is
    for behavior
        for U_PASSIVE_TEST : PASSIVE_TEST use entity work.passive_test(BEHAVIOR2);
        end for;
    end for;
end PASSIVE_TEST_CONFIG2;

entity DD_TEST is
end DD_TEST;

architecture behavior  of DD_TEST is

    signal  CLK0    : std_logic;
    signal  CLK1    : std_logic;
    signal  COUNT   : std_logic_vector(3 downto 0) := (others => '0');
    signal  CNT_OK  : std_logic_vector(3 downto 0) := (others => '0');
    signal  CNT_NG  : std_logic_vector(3 downto 0) := (others => '0');

begin

    -- クロック生成
    process begin
        CLK0 <= '0';
        wait for 10 ns;
        CLK0 <= '1';
        wait for 10 ns;
    end process;

    -- クロックを複製
    CLK1 <= CLK0;

    -- CLK0でCOUNTをインクリメント
    process ( CLK0 ) begin
        if ( CLK0'event and CLK0 = '1' ) then
            COUNT <= COUNT + '1';
        end if;
    end process;

    -- COUNTをCLK0で１段遅らせる
    process ( CLK0 ) begin
        if ( CLK0'event and CLK0 = '1' ) then
            CNT_OK <= COUNT;
        end if;
    end process;

    -- COUNTをCLK1で１段遅らせる
    process ( CLK1 ) begin
        if ( CLK1'event and CLK1 = '1' ) then
            CNT_NG <= COUNT;
        end if;
    end process;

end behavior ;

library unisim;
use unisim.vcomponents.all;

-- クロックバッファを入れてクロックイネーブルを生成するモジュール
entity CLKGEN is
    port
    (
        CLK_IN      : in    std_logic;
        CLK_OUT     : out   std_logic;
        CKE         : out   std_logic
    );
end CLKGEN;

architecture behavior  of CLKGEN is

    signal  CLK_BUFF    : std_logic;
    signal  COUNT       : std_logic_vector(3 downto 0) := (others => '0');

begin

    -- Ｘｉｌｉｎｘのグローバルクロックバッファ
    U_BUFG : BUFG port map ( I => CLK_IN, O => CLK_BUFF );
    -- ＶＨＤＬの制約（portでoutに指定した信号は内部で参照出来ない）のため、
    -- クロックイネーブルを作るクロックを一度、ローカル信号に入れる。

    -- クロックの出力
    CLK_OUT <= CLK_BUFF;

    -- クロックイネーブルを作るためのカウンタ
    process ( CLK_BUFF ) begin
        if ( CLK_BUFF'event and CLK_BUFF = '1' ) then
            COUNT <= COUNT + '1';
        end if;
    end process;

    -- クロックイネーブル
    process ( CLK_BUFF ) begin
        if ( CLK_BUFF'event and CLK_BUFF = '1' ) then
            if ( COUNT = (COUNT'range => '0') ) then
                CKE <= '1';
            else
                CKE <= '0';
            end if;
        end if;
    end process;

end behavior ;

-- １６Ｗｏｒｄｘ８Ｂｉｔｘ４Ｂａｎｋｓの同期メモリ
entity test_accs is
    port
    (
        CLK         : in    std_logic;                      -- クロック
        RST         : in    std_logic;                      -- リセット
        ADDR        : in    std_logic_vector(3 downto 0);   -- アドレス(16Word=4Bit)
        BA          : in    std_logic_vector(1 downto 0);   -- バンクアドレス(4Bank=2Bit)
        CS          : in    std_logic;                      -- チップセレクト
        WE          : in    std_logic;                      -- ライトイネーブル
        INDATA      : in    std_logic_vector(7 downto 0);   -- ライトデータ
        OUTDATA     : out   std_logic_vector(7 downto 0)    -- リードデータ
    );
end test_accs;

architecture behavior of test_accs is

    -- データ幅８Ｂｉｔのサブタイプ
    subtype BUSWIDS     is std_logic_vector(7 downto 0);
    -- １６Ｗｏｒｄのサブタイプ
    subtype ARRAYNUM    is std_logic_vector(15 downto 0);
    -- １Ｂａｎｋのデータタイプ
    type    CELLARRAY   is array(ARRAYNUM'range) of BUSWIDS;
    -- １Ｂａｎｋのアクセスタイプ（ポインタ）
    type    BNKACCESS   is access CELLARRAY;
    -- １Ｂａｎｋのアクセスタイプの４配列（ポインタの配列）
    type    BNKARRAY    is array(3 downto 0) of BNKACCESS;

begin

    process
        -- アクセスタイプの４配列をインスタンス
        variable    BANK        : BNKARRAY := (others => NULL);

        variable    BA_INT      : integer;
        variable    ADDR_INT    : integer;
    begin

        -- クロックの立ち上がりエッジで動作する
        wait until CLK = '1';

        -- データ型変換
        BA_INT := conv_integer(BA);
        ADDR_INT := conv_integer(ADDR);

        -- チップセレクトがイネーブルで選択されているバンクに
        -- メモリが割り当たっていない場合
        if ( RST = '0' and CS = '1' and BANK(BA_INT) = NULL ) then
            -- 選択されているバンクにメモリを確保する
            BANK(BA_INT) := new CELLARRAY;
            -- 確保したメモリ領域を０クリアする
            for i in ARRAYNUM'range loop
                BANK(BA_INT)(i) := BUSWIDS'(others => '0');
            end loop;
        end if;

        -- チップセレクトがイネーブルでライトイネーブルがイネーブルの場合
        if ( RST = '0' and CS = '1' and WE = '1' ) then
            -- メモリにデータを書き込む
            BANK(BA_INT)(ADDR_INT) := INDATA;
        end if;

        -- チップセレクトがイネーブルの場合
        if ( RST = '0' and CS = '1' ) then
            -- メモリからデータを読み出す
            OUTDATA <= BANK(BA_INT)(ADDR_INT);

        -- チップセレクトがイネーブルでない場合
        else
            -- データを弱いＨＩＧＨ（プルアップ）にする
            OUTDATA <= (others => 'H');
        end if;

        -- リセットがイネーブルの場合
        if ( RST = '1' ) then
            -- メモリ割り当てを解放する
            for i in BNKARRAY'range loop
                if ( BANK(i) /= NULL ) then
                    deallocate(BANK(i));
                    BANK(i) := NULL;
                end if;
            end loop;
        end if;

    end process;

end behavior;

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;

library c;
use c.stdio_h.all;

library modelsim_lib;
use modelsim_lib.util.all;

entity test_printf is
end test_printf;

architecture behavior of test_printf is
    signal STV8 : std_logic_vector(7 downto 0);
begin

    process begin
  -- これはＭｏｄｅｌＳｉｍのファンクション
        signal_force( "STV8", "00000000", 0 ns, deposit, -1 ms, 0  );
        wait;
    end process;

    process begin
        wait for 100 ns;
        STV8 <= STV8 + '1';
        printf("abc");
        printf("def\n");
        printf("std_logic_vector=0x%x(%d)\n", STV8, STV8);
    end process;
end behavior;

entity ANALOG_SW is
    port
    (
        PORTA           : inout std_logic;
        PORTB           : inout std_logic;
        CONTROL         : in    std_logic
    );
end ANALOG_SW;

architecture BEHAVIOR of ANALOG_SW is

begin

    PROCESS
        VARIABLE last_time : time;
    BEGIN
            WAIT ON PORTA'TRANSACTION, PORTB'TRANSACTION,
                    CONTROL'TRANSACTION UNTIL last_time /= NOW;
            last_time := NOW;
            PORTA <= 'Z';
            PORTB <= 'Z';
            WAIT FOR 0 ns;

            if ( CONTROL = '1' ) then
                PORTA <= PORTB;
                PORTB <= PORTA;
            end if;
    END PROCESS;

end BEHAVIOR;

entity BITDELAY is
   generic
   (
       -- 呼び側で指定されないときのディフォルト値を指定できる --
       COUNT : integer := 4
   );
   port
   (
       CLK    : in  STD_LOGIC;
       RST    : in  STD_LOGIC;
       CKE    : in  STD_LOGIC;
       DIN    : in  STD_LOGIC;
       DOUT   : out STD_LOGIC
   );
end BITDELAY;

architecture rtl of BITDELAY is

signal L_DELBUFF : std_logic_vector(0 to COUNT-1);

begin

    process ( RST, CLK ) begin
       if ( RST = '1' ) then
           for LPCNT in 0 to COUNT-1 loop
               L_DELBUFF(LPCNT) <= '0';
           end loop;
       elsif ( CLK'event and CLK = '1' ) then
           if ( CKE = '1' ) then
               L_DELBUFF(0) <= DIN;
               for LPCNT in 1 to COUNT-1 loop
                   L_DELBUFF(LPCNT) <= L_DELBUFF(LPCNT-1);
               end loop;
           end if;
       end if;
   end process;
   DOUT <= L_DELBUFF(COUNT-1);

end rtl;

-- 信号宣言 --
signal SDRAM_CONT1 : SDRAM_IF;
signal SDRAM_CONT2 : SDRAM_IF;
signal RF_CMD : std_logic_vector(3 downto 0);

-- 以下使用方法 --
process ( RST, CLK ) begin
    if ( RST = '1' ) then
        -- カンマで分けて一度に代入することも出来る --
        SDRAM_CONT2 <= ((others => '0'), (others => '0'), '0',
                        '0', '0', '0', '0', (others => '0'));
    elsif ( CLK'event and CLK = '1' ) then
        -- 同じデータタイプは一度に全て代入できる --
        SDRAM_CONT2 <= SDRAM_CONT1;
    end if;
end process;

-- 信号名と要素をピリオドで各要素に代入できる --
SDRAM_CONT1.CS_N <= RF_CMD(0);
SDRAM_CONT1.RAS_N <= RF_CMD(1);
SDRAM_CONT1.CAS_N <= RF_CMD(2);
SDRAM_CONT1.WE_N <= RF_CMD(3);

    -- 信号宣言 --
    signal ABUS : std_logic_vector(31 downto 0);
    signal RES : std_logic;

    -- リダクション演算 --
    RES <= and_reduce(ABUS);

    signal TEST : std_logic_vector(TVS-1 downto 0);

    if ( TEST = (TEST'range => '1') ) then
        TEST <= TEST + '1';
    end if;