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ʪÍý¥¿¥¤¥×¤È¤Ï¡¢»þ´Ö¤äÅ۵¡¢ÅÅή¡¢µ÷Î¥¤Ê¤É¤ÎʪÍýŪ¤Êʪ¤òɽ¤¹¤¿¤á¤Ë»ÈÍѤ¹¤ë¥Ç¡¼¥¿¥¿¥¤¥×¤À¡£
£Ö£È£Ä£Ì¤Ë¤Ï¸µ¡¹¡Ö£ô£é£í£å¡×¤¬ÊªÍý¥¿¥¤¥×¤È¤·¤ÆÄêµÁ¤µ¤ì¤Æ¤ª¤êÆâÍÆ¤Ï¥¹¥¿¥ó¥À¡¼¥É¥Ñ¥Ã¥±¡¼¥¸¤Ë½ñ¤«¤ì¤Æ¤¤¤ë¡£
¤³¤Î¡Ö£ô£é£í£å¡×¤òÂåɽ¤È¤¹¤ëʪÍý¥¿¥¤¥×¤Ï£ð£ó¤ä£î£ó¤Ê¤É¤Îñ°Ì¤ò»ØÄê¤Ç¤¤ë¤Î¤¬Âç¤¤ÊÆÃħ¤Ç¡¢¿·¤·¤¤Ã±°Ì¤ò»ý¤Ã¤¿¥Ç¡¼¥¿¥¿¥¤¥×¤òºîÀ®¤¹¤ë»ö¤â½ÐÍè¤ë¡£
°Ê²¼¤ÎÎã¤Ïµ÷Î¥¤ÎʪÍý¥¿¥¤¥×¤ò¿·¤¿¤ËÄêµÁ¤·¤Æ¡¢¤½¤Îµ÷Î¥¤òÃÙ±ä»þ´Ö¤ËÊÑ´¹¤¹¤ë´Ø¿ô¤âÍѰդ·¤¿¡£¡ÊÃÙ±ä»þ´Ö¤Ï£±£î£ó¡á£±£µ£ã£í¤Ç·×»»¡Ë
use modelsim_lib.util.all;
package distance_pkg is
-- µ÷Î¥¥¿¥¤¥×
type distance is range 0 to integer'high
units
munit;
um = 10 munit;
mm = 1000 um;
cm = 10 mm;
m = 100 cm;
km = 1000 m;
mil = 254 munit;
inch = 1000 mil;
ft = 12 inch;
yd = 3 ft;
fm = 6 ft;
mi = 5280 ft;
lg = 3 mi;
end units;
-- µ÷Î¥¤«¤éÃÙ±ä»þ´Ö¤ò»»½Ð
function distance2time( trace_len : distance ) return time;
end distance_pkg;
package body distance_pkg is
-- µ÷Î¥¤«¤éÃÙ±ä»þ´Ö¤ò»»½Ð
function distance2time( trace_len : distance ) return time is
variable resolution : real;
variable delay_time : time;
begin
-- ¥·¥ß¥å¥ì¡¼¥·¥ç¥ó¥ì¥¾¥ê¥å¡¼¥·¥ç¥ó¤Î¼èÆÀ
resolution := get_resolution;
-- ¥á¡¼¥È¥ë¡Ý»þ´ÖÊÑ´¹
--1ns=15cm(150000um)
--1000000fs=150000um
--1fs=0.15um(1.5munit)
delay_time := to_time( real( distance'pos(trace_len))
/(1.5 * resolution * 1000000000000000.0));
return delay_time;
end;
end distance_pkg;
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¥Ç¡¼¥¿¤À¤±¤Ç¤âÉü³è¤µ¤»¤è¤¦¤È»î¤»¤ë»ö¤Ï»³¤Û¤É¤ä¤Ã¤Æ¤ß¤¿¤¬¤ä¤Ã¤Ñ¤ê̵Íý¤À¤Ã¤¿¡£¤½¤·¤ÆÄ´¤Ù¤Æ¤¤¤¯¤¦¤Á¤Ë¥¨¥é¡¼¤Î¸¶°ø¤Ï¤É¤¦¤ä¤é£È£Ä£Ä¤Ë¤¢¤ë»ö¤¬Ê¬¤«¤Ã¤¿¡£
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2007ǯ09·î26Æü
VHDL TIPS ¡ÖÁÐÊý¸þ¥Ð¥¹¤ÎÃÙ±ä¥â¥Ç¥ë¡×
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¤³¤ÎPORTA¤ÈPORTB¤ËÂФ·¤Æ¥Æ¥¹¥È¥Ù¥ó¥Á¤«¤éÇÈ·Á¤òÆþÎϤ¹¤ë¡£

ÇÈ·Á¤òÆþÎϤ¹¤ë¥Æ¥¹¥È¥Ù¥ó¥Á¤Ï¤³¤ì¡£
use IEEE.std_logic_1164.all;
entity TEST is
end TEST;
architecture BEHAVIOR of TEST is
component LINEDELAY
generic
(
linedelay : time
);
port
(
PORTA : inout std_logic;
PORTB : inout std_logic
);
end component;
signal PORTA : std_logic;
signal PORTB : std_logic;
signal PORTA_S : std_logic;
signal PORTB_S : std_logic;
begin
C_LINEDELAY : LINEDELAY
generic map
(
linedelay => 10 ns
)
port map
(
PORTA => PORTA_S,
PORTB => PORTB_S
);
process begin
PORTA <= 'Z';
PORTB <= 'Z';
wait for 100 ns;
PORTA <= '1';
wait for 100 ns;
PORTA <= '0';
wait for 100 ns;
PORTA <= 'Z';
PORTB <= '1';
wait for 100 ns;
PORTB <= '0';
wait for 100 ns;
PORTB <= 'Z';
wait for 100 ns;
PORTA <= '1';
PORTB <= '0';
wait for 100 ns;
PORTA <= '0';
PORTB <= '1';
wait for 100 ns;
PORTA <= '1';
wait for 100 ns;
PORTA <= '0';
PORTB <= '0';
wait for 100 ns;
end process;
PORTA_S <= PORTA;
PORTB_S <= PORTB;
end BEHAVIOR;
¤½¤·¤ÆÆ°ºî·ë²Ì¤ÎÇÈ·Á¤Ï¤³¤ó¤Ê´¶¤¸¡£

PORTA¤«¤é½ÐÎϤ·¤¿Ãͤϡ¢¤¹¤°¤ËPORTA_S¤ËÈ¿±Ç¤µ¤ì¤ë¤¬PORTB_S¤Ë¤ÏÃٱ䤬Æþ¤Ã¤Æ¤¤¤ë»ö¤¬Ê¬¤«¤ë¡£
µÕ¤ËPORTB¤«¤é½ÐÎϤ·¤¿Ãͤϡ¢¤¹¤°¤ËPORTB_S¤ËÈ¿±Ç¤µ¤ì¤ë¤¬PORTA_S¤Ë¤ÏÃٱ䤬Æþ¤Ã¤Æ¤¤¤ë¡£
¤Þ¤¿¡¢Æ±»þ¤ËPORTA_S¤ÈPORTB_S¤ÎÃͤòÊѲ½¤µ¤»¤Æ¤âÃÙ±ä»þ´Öʬ¤Î¥·¥ç¡¼¥È¤¬'X'¤ÇºÆ¸½¤µ¤ì¤Æ¤¤¤ë¡£
¼¡¤Ë´Î¿´¤Ê¥â¥Ç¥ë¤Î¥½¡¼¥¹¤¬¤³¤ì¡£
use IEEE.std_logic_1164.all;
entity LINEDELAY is
generic
(
linedelay : time
);
port
(
PORTA : inout std_logic;
PORTB : inout std_logic
);
end LINEDELAY;
architecture BEHAVIOR of LINEDELAY is
signal PORTA_X : std_logic;
signal PORTB_X : std_logic;
begin
PROCESS
VARIABLE last_time : time;
VARIABLE transact : boolean;
BEGIN
WAIT ON PORTA'TRANSACTION, PORTB_X UNTIL (last_time /= NOW or PORTB_X'EVENT);
if ( PORTA'TRANSACTION'EVENT ) then
PORTA <= 'Z';
transact := TRUE;
last_time := NOW;
else
transact := FALSE;
end if;
WAIT FOR 0 ns;
if ( transact = TRUE ) then
PORTA_X <= transport PORTA after linedelay;
end if;
PORTA <= PORTB_X;
END PROCESS;
PROCESS
VARIABLE last_time : time;
VARIABLE transact : boolean;
BEGIN
WAIT ON PORTB'TRANSACTION, PORTA_X UNTIL (last_time /= NOW or PORTA_X'EVENT);
if ( PORTB'TRANSACTION'EVENT ) then
PORTB <= 'Z';
last_time := NOW;
transact := TRUE;
else
transact := FALSE;
end if;
WAIT FOR 0 ns;
if ( transact = TRUE ) then
PORTB_X <= transport PORTB after linedelay;
end if;
PORTB <= PORTA_X;
END PROCESS;
end BEHAVIOR;
PORTA_X¤ÈPORTB_X¤Ë¡¢¤½¤ì¤¾¤ì¤ÎÁÐÊý¸þ¥Ý¡¼¥È¤ÎÃͤò¥³¥Ô¡¼¤·¡¢¤½¤ì¤òÃٱ䤵¤»¤ÆÈ¿ÂЦ¤Î¥Ý¡¼¥È¤ËÂåÆþ¤·¤Æ¤¤¤ë¡£
¤³¤ÎÁÐÊý¸þ¥Ý¡¼¥È¤ÎÃͤò¥³¥Ô¡¼¤¹¤ë»þ¡¢°ìÅÙ¥â¥Ç¥ë¦¤Î¥É¥é¥¤¥Ð¤ò'Z'¤Ë¤·¤ÆËÜÅö¤ÎÁê¼ê¦¥Ý¡¼¥È¤ÎÃͤò¼èÆÀ¤¹¤ëɬÍפ¬¤¢¤ë¡£
¤Þ¤¿¡¢ÊѤʡÖWAITʸ¡×¡¢¤³¤ì¤ÏÁÐÊý¸þ¥Ý¡¼¥È¤Î¥È¥é¥ó¥¶¥¯¥·¥ç¥ó¤Ï»þ´Öñ°Ì¤¢¤¿¤ê£±ÅÙ¤·¤«Æ°ºî¤µ¤»¤¿¤¯Ìµ¤¤¤Î¤ËÂФ·È¿ÂЦ¤ÎÁÐÊý¸þ¥Ý¡¼¥È¤ò¥³¥Ô¡¼¤·¤¿ÃͤΥ¤¥Ù¥ó¥È¤Ï²¿²ó¤Ç¤âưºî¤µ¤»¤ë¤¿¤á¤Î¾ò·ï¤À¡£
ÁÐÊý¸þ¥Ý¡¼¥È¤Î¥È¥é¥ó¥¶¥¯¥·¥ç¥ó¤ò»þ´Öñ°Ì¤¢¤¿¤ê£±ÅÙ¤·¤«Æ°ºî¤µ¤»¤¿¤¯¤Ê¤¤Íýͳ¤Ï¡¢¼«Ê¬¤Ç¥È¥é¥ó¥¶¥¯¥·¥ç¥ó¤òȯÀ¸¤µ¤»¤Æ¤¤¤ë¤¿¤á¤³¤Î¾ò·ï¤¬Ìµ¤¤¤È¥ë¡¼¥×¤Ë´Ù¤Ã¤Æ¤·¤Þ¤¦¤«¤é¤Ç¤¢¤ë¡£
¤¿¤À¡¢ÁÐÊý¸þ¥Ý¡¼¥È¤Î°ìÈֺǽé¤Î¥È¥é¥ó¥¶¥¯¥·¥ç¥ó¤Çưºî¤µ¤»¤Æ¤¤¤ë¤¿¤á¡¢¥È¥é¥ó¥¶¥¯¥·¥ç¥ó¤¬È¯À¸¤·¤¿¥Ç¥ë¥¿»þ´Ö¤Î¸å¤Î¥Ç¥ë¥¿»þ´Ö¤ËÃͤ¬ÊѲ½¤¹¤ë¤è¤¦¤Ê¿®¹æ¤Ç¤Ï¤¦¤Þ¤¯Æ°ºî¤·¤Ê¤¤¡£
¾°¡¢°ÊÁ°¾Ò²ð¤·¤¿VHDL TIPS ¡Ö¥¢¥Ê¥í¥°¥¹¥¤¥Ã¥Á¤Î¥â¥Ç¥ê¥ó¥°¡×¤â¤½¤¦¤À¤¬¡¢¤³¤Î¼ê¤Î¼êË¡¤Ï¤³¤ÎÀ©¸Â¤¬¤Ä¤¤Þ¤È¤Ã¤Æ¤·¤Þ¤¦¡£
2007ǯ09·î21Æü
VHDL TIPS ¡Ö°À"DRIVING_VALUE"¤Î»ÈÍÑË¡¡×
£Ö£È£Ä£Ì¤Ç¤Ï½ÐÎϥݡ¼¥È¤Ë³ä¤êÅö¤Æ¤¿ÃͤòÆâÉô¤Ç»²¾È¤¹¤ë»ö¤Ï½ÐÍè¤Ê¤¤¡£
½ê¤¬¡¢£Ö£È£Ä£Ì£¹£³¤Ç¥³¥ì¤ò²Äǽ¤Ë¤¹¤ë¥¢¥È¥ê¥Ó¥å¡¼¥È¡ÖDRIVING_VALUE¡×¤¬Äɲ䵤줿¡£
°Ê²¼¤Ë»ÈÍÑÎã¤ò¾Ò²ð¤¹¤ë¡£
use IEEE.std_logic_1164.all;
use IEEE.std_logic_signed.all;
entity COUNT is
port
(
CLK : in std_logic;
COUNT : out std_logic_vector(7 downto 0) := (others => '0')
);
end COUNT;
architecture rtl of COUNT is
begin
process ( CLK ) begin
if ( CLK'event and CLK = '1' ) then
COUNT <= COUNT'DRIVING_VALUE + '1'; -- ÆâÉô»²¾È
end if;
end process;
end rtl;
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µÞ¢£É£Ó£Å£¹¡¥£²¤ò»È¤¦É¬Íפ¬½Ð¤Æ¤¤¿¡£
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VHDL TIPS ¡Öshared variable¤Î»ÈÍÑË¡¡×
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shared variable SH_INT : integer;
end shared_pkg;
library IEEE;
use IEEE.std_logic_1164.all;
library work;
use work.shared_pkg.all;
entity a is
port
(
CLK : in std_logic;
DATA : out integer
);
end a;
architecture a of a is
component b
port
(
CLK : in std_logic
);
end component;
begin
u_b : b port map( CLK );
process ( CLK ) begin
if ( CLK'event and CLK = '1' ) then
DATA <= SH_INT;
end if;
end process;
end a;
library IEEE;
use IEEE.std_logic_1164.all;
library work;
use work.shared_pkg.all;
entity b is
port
(
CLK : in std_logic
);
end b;
architecture b of b is
begin
process ( CLK ) begin
if ( CLK'event and CLK = '1' ) then
SH_INT := SH_INT + 1;
end if;
end process;
end b;
¤³¤ÎÎã¤Ç¤Ï¡¢£²¤Ä¤Î¥¢¡¼¥¥Æ¥¯¥Á¥ã¤«¤é¥Ñ¥Ã¥±¡¼¥¸¤ÇÀë¸À¤·¤¿¶¦ÍÊÑ¿ô¤Ë¥¢¥¯¥»¥¹¤·¤Æ¤¤¤ë¡£
¼¡¤Ë¡¢£Ö£È£Ä£Ì£²£°£°£²¤ÎÎã
type SH_TEST is protected
-- ½ñ¤¹þ¤ß´Ø¿ô
procedure write ( data : in integer );
-- ÆÉ¤ß½Ð¤·´Ø¿ô
impure function read return integer;
end protected SH_TEST;
-- ¶¦ÍÊÑ¿ô¤ò¥×¥í¥Æ¥¯¥È¥¿¥¤¥×¤ÇÀë¸À
shared variable SH_INT : SH_TEST;
end shared_pkg;
package body shared_pkg is
type SH_TEST is protected body
-- ¼Â¥Ç¡¼¥¿
variable buf : integer := 0;
-- ½ñ¤¹þ¤ß´Ø¿ô
procedure write ( data : in integer ) is
begin
buf := data;
end;
-- ÆÉ¤ß½Ð¤·´Ø¿ô
impure function read return integer is
begin
return buf;
end;
end protected body SH_TEST;
end shared_pkg;
library IEEE;
use IEEE.std_logic_1164.all;
library work;
use work.shared_pkg.all;
entity a is
port
(
CLK : in std_logic;
DATA : out integer
);
end a;
architecture a of a is
component b
port
(
CLK : in std_logic
);
end component;
begin
process ( CLK ) begin
if ( CLK'event and CLK = '1' ) then
DATA <= SH_INT.read;
end if;
end process;
u_b : b port map( CLK );
end a;
library IEEE;
use IEEE.std_logic_1164.all;
library work;
use work.shared_pkg.all;
entity b is
port
(
CLK : in std_logic
);
end b;
architecture b of b is
begin
process ( CLK ) begin
if ( CLK'event and CLK = '1' ) then
SH_INT.write( SH_INT.read + 1 );
end if;
end process;
end b;
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library IEEE;
use IEEE.std_logic_1164.all;
-- £Æ£Ð£Ç£Á¤Î¥È¥Ã¥×¥Õ¥¡¥¤¥ë¤Ë¤³¤Î¥Ñ¥Ã¥±¡¼¥¸¤òÀë¸À¤¹¤ë¡£
library work;
use work.ver_get.all;
entity top is
generic
(
-- ¥·¥ß¥å¥ì¡¼¥·¥ç¥ó¤ò¹Ô¤¦¾ì¹ç¤Ï¡¢
-- ¥Æ¥¹¥È¥Ù¥ó¥Á¤«¤é¡ÖSIM_MODE¡×¤ò1¤Ë¤·¤Æ¸Æ¤Ó½Ð¤¹¡£
-- ¹çÀ®¤Î»þ¤Ï¥Ç¥£¥Õ¥©¥ë¥È¤Î0¤¬¼«Æ°Åª¤Ë³ä¤êÅö¤¿¤ë¡£
SIM_MODE : integer := 0
);
port
(
VER_OUT : out std_logic_vector(31 downto 0)
);
end top;
architecture top of top is
-- ¤³¤Î¸Æ¤Ó½Ð¤·¤ÇÏÀÍý¹çÀ®¤¹¤ëËè¤Ë¥¤¥ó¥¯¥ê¥á¥ó¥È¤µ¤ì¤¿ÃͤòÊÖ¤¹¡£
constant VERSION : std_logic_vector(31 downto 0)
:= get_version( SIM_MODE, "ver.txt" );
begin
VER_OUT <= VERSION;
end top;
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