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2007ǯ10·î05Æü

¿·¥×¥í¥¸¥§¥¯¥È

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º£¸å¤â£Â£Ì£Ï£Ç¹¹¿·¤Î¥Ú¡¼¥¹¤Ï¾å¤¬¤é¤Ê¤¤¤È»×¤¦¤¬¡¢¤Ê¤ë¤Ù¤¯µ»½ÑŪ¤Ê¾ðÊó¤òÅê¹Æ¤·¤Æ¤¤¤­¤¿¤¤¤È»×¤¦¡£¡ÊÍèǯ²Æº¢¤Ë¤Ï²òÊü¤µ¤ì¤ëͽÄê¡¥¡¥¡¥¡Ë



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2007ǯ10·î02Æü

VHDL TIPS ¡ÖʪÍý¥¿¥¤¥×¤Î»È¤¤Êý¡×

ʪÍý¥¿¥¤¥×¤È¤Ï¡¢»þ´Ö¤äÅ۵¡¢ÅÅή¡¢µ÷Î¥¤Ê¤É¤ÎʪÍýŪ¤Êʪ¤òɽ¤¹¤¿¤á¤Ë»ÈÍѤ¹¤ë¥Ç¡¼¥¿¥¿¥¤¥×¤À¡£
£Ö£È£Ä£Ì¤Ë¤Ï¸µ¡¹¡Ö£ô£é£í£å¡×¤¬ÊªÍý¥¿¥¤¥×¤È¤·¤ÆÄêµÁ¤µ¤ì¤Æ¤ª¤êÆâÍÆ¤Ï¥¹¥¿¥ó¥À¡¼¥É¥Ñ¥Ã¥±¡¼¥¸¤Ë½ñ¤«¤ì¤Æ¤¤¤ë¡£
¤³¤Î¡Ö£ô£é£í£å¡×¤òÂåɽ¤È¤¹¤ëʪÍý¥¿¥¤¥×¤Ï£ð£ó¤ä£î£ó¤Ê¤É¤Îñ°Ì¤ò»ØÄê¤Ç¤­¤ë¤Î¤¬Â礭¤ÊÆÃħ¤Ç¡¢¿·¤·¤¤Ã±°Ì¤ò»ý¤Ã¤¿¥Ç¡¼¥¿¥¿¥¤¥×¤òºîÀ®¤¹¤ë»ö¤â½ÐÍè¤ë¡£

°Ê²¼¤ÎÎã¤Ïµ÷Î¥¤ÎʪÍý¥¿¥¤¥×¤ò¿·¤¿¤ËÄêµÁ¤·¤Æ¡¢¤½¤Îµ÷Î¥¤òÃÙ±ä»þ´Ö¤ËÊÑ´¹¤¹¤ë´Ø¿ô¤âÍѰդ·¤¿¡£¡ÊÃÙ±ä»þ´Ö¤Ï£±£î£ó¡á£±£µ£ã£í¤Ç·×»»¡Ë


library modelsim_lib;
use modelsim_lib.util.all;

package distance_pkg is

    -- µ÷Î¥¥¿¥¤¥×
    type distance is range 0 to integer'high
        units
            munit;

            um      = 10 munit;
            mm      = 1000 um;
            cm      = 10 mm;
            m       = 100 cm;
            km      = 1000 m;

            mil     = 254 munit;
            inch    = 1000 mil;
            ft      = 12 inch;
            yd      = 3 ft;
            fm      = 6 ft;
            mi      = 5280 ft;
            lg      = 3 mi;
        end units;

    -- µ÷Î¥¤«¤éÃÙ±ä»þ´Ö¤ò»»½Ð
    function distance2time( trace_len : distance ) return time;

end distance_pkg;

package body distance_pkg is

    -- µ÷Î¥¤«¤éÃÙ±ä»þ´Ö¤ò»»½Ð
    function distance2time( trace_len : distance ) return time is
        variable    resolution      : real;
        variable    delay_time      : time;
    begin
        -- ¥·¥ß¥å¥ì¡¼¥·¥ç¥ó¥ì¥¾¥ê¥å¡¼¥·¥ç¥ó¤Î¼èÆÀ
        resolution := get_resolution;

        -- ¥á¡¼¥È¥ë¡Ý»þ´ÖÊÑ´¹
        --1ns=15cm(150000um)
        --1000000fs=150000um
        --1fs=0.15um(1.5munit)
        delay_time := to_time( real( distance'pos(trace_len))
                                 /(1.5 * resolution * 1000000000000000.0));

        return delay_time;
    end;

end distance_pkg;


¤³¤Î¤è¤¦¤ËºÇ¾®Ã±°Ì¤«¤é¤Î·¸¿ô¤òÊѤ¨¤ë¤³¤È¤Ç¡¢¥ß¥ê¤ä¥¤¥ó¥Á¤Ê¤É¤òº®ºß¤·¤Æµ­½Ò½ÐÍè¤ë»ö¤âÊØÍø¤ÊÅÀ¤À¡£
¤Þ¤¿¡¢µ÷Î¥¤òÃÙ±ä»þ´Ö¤ËÊÑ´¹¤¹¤ë´Ø¿ô¤Ï¡¢¡Ö£ô£é£í£å¡×¤¬¥·¥ß¥å¥ì¡¼¥·¥ç¥ó¤Î¥ì¥¾¥ê¥å¡¼¥·¥ç¥ó¤Ë¤è¤Ã¤ÆºÇ¾®Ã±°Ì¤¬ÊѤï¤ëÆÃ¼ì¤ÊʪÍý¥¿¥¤¥×¤Î¤¿¤á¡¢¤Þ¤º¥ì¥¾¥ê¥å¡¼¥·¥ç¥ó¤ò¼èÆÀ¤·¤Æ¤«¤éÊÑ´¹¤·¤Æ¤¤¤ë¡£

¤³¤Îµ÷Î¥¥Ñ¥Ã¥±¡¼¥¸¤ò»È¤¦¤È¡¢°ÊÁ°¾Ò²ð¤·¤¿VHDL TIPS ¡ÖÁÐÊý¸þ¥Ð¥¹¤ÎÃÙ±ä¥â¥Ç¥ë¡×¤ÎÃÙ±äÃͤòÆþÎϤ¹¤ëÉôʬ¤ò¡¢µ÷Î¥¤òÆþÎϤ¹¤ëÍͤ˴Êñ¤ËÃÖ¤­´¹¤¨¤ë¤³¤È¤¬½ÐÍè¤ë¤Î¤Ç¡¢¥±¡¼¥Ö¥ë¤Î¥â¥Ç¥ê¥ó¥°¤Ê¤É¤Ë»ÈÍѤ¹¤ë¤È¤ª¤â¤·¤í¤¤¤È»×¤¦¡£



Åê¹Æ»þ¹ï(08:58)¨¢¥³¥á¥ó¥È(0)¨¢VHDL 

2007ǯ09·î29Æü

£Ð£Ã¸Î¾ã¡ª

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Åê¹Æ»þ¹ï(22:27)¨¢¥³¥á¥ó¥È(2)¨¢Æüµ­ 

2007ǯ09·î28Æü

ChipScope¤â¤É¤­¡©

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¤Ç¤â¡¢£Ã£è£é£ð£Ó£ã£ï£ð£å¤Þ¤Ç¤Îµ¡Ç½¤¬¤¢¤ë¤È¤Ï»×¤¨¤Ê¤¤¤Î¤Ç¡¢¸½¾õ¥³¥ì¤ò»î¤½¤¦¤È¤Ï»×¤ï¤Ê¤¤¤¬¥½¡¼¥¹¥³¡¼¥É¡Ê»Äǰ¤Ê¤¬¤é£ö£å£ò£é£ì£ï£ç¡Ë¤¬¸ø³«¤µ¤ì¤Æ¤¤¤ë¤Î¤Ç£Ã£è£é£ð£Ó£ã£ï£ð£å¤Ç¤Ï½ÐÍè¤Ê¤¤»ö¤¬½Ð¤Æ¤­¤¿¾ì¹ç¡¢¥³¥ì¤ò¥Ù¡¼¥¹¤Ëºî¤ê¹þ¤à»ö¤Ï½ÐÍè¤ë¤È»×¤¦¡£
¤Þ¤¿¡¢£Ã£è£é£ð£Ó£ã£ï£ð£å¤ò¸Ä¿Í¤Ç¹ØÆþ¤¹¤ë¿Í¤Ï¾¯¤Ê¤¤¤È»×¤¦¤¬¡¢¥³¥ì¤Ï£Ç£Ð£Ì¤Ê¤Î¤Ç¡¢¤ª¶â¤¬¤«¤«¤é¤Ê¤¯¤Æ¤¹¤à¡£

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Åê¹Æ»þ¹ï(20:21)¨¢¥³¥á¥ó¥È(0)¨¢»¨µ­ 

2007ǯ09·î26Æü

VHDL TIPS ¡ÖÁÐÊý¸þ¥Ð¥¹¤ÎÃÙ±ä¥â¥Ç¥ë¡×

£Æ£Ð£Ç£Á¤È¥á¥â¥ê¥â¥Ç¥ë¤òÀܳ¤¹¤ë¾ì¹çÅù¤Ë¡ÖÁÐÊý¸þ¥Ð¥¹¤Ç¥Í¥Ã¥È¤ÎÃÙ±ä¤òÁÞÆþ¤·¤¿¤¤¡×¤È»×¤Ã¤¿»ö¤¬²¿ÅÙ¤«¤¢¤ë¡£
°Âľ¤Ë¡Öafterʸ¡×¤Ç¤ª¸ß¤¤¤òÂåÆþ¤·¤Æ¤â'X'¤Ë¤Ê¤Ã¤¿°Ê¹ß¤Ï¤º¤Ã¤È'X'¤Î¤Þ¤Þ¤Ç¤¦¤Þ¤¯¤¤¤«¤Ê¤¤¡£
¤Ç¤Ï¤É¤¦¤¹¤ì¤ÐÁÐÊý¸þ¥Ð¥¹¤ËÃÙ±ä¤òÁÞÆþ¤¹¤ë»ö¤¬½ÐÍè¤ë¤Î¤À¤í¤¦¤«¡©
´Êñ¤ÊÍͤǡ¢¤³¤ì¤¬·ë¹½Æñ¤·¤¤¡£¿§¡¹¤È¹Í¤¨¤¿Ëö¤Ë¡¢ÁÐÊý¸þ¥Ð¥¹¤ÎÃÙ±ä¥â¥Ç¥ë¤òºîÀ®¤Ç¤­¤¿¤Î¤Ç¾Ò²ð¤¹¤ë¡£

¤Þ¤º¤Ï¡¢¥â¥Ç¥ë¤Îưºî¤ò³Îǧ¤·¤¿²óÏ©¡£
ÁÐÊý¸þ¤ÎÃÙ±ä¥â¥Ç¥ë¤À¤¬¡¢¥Æ¥¹¥È¤ÇÆþÎϤϻÈÍѤ·¤Ê¤¤¤Î¤Ç½ÐÎϤΤߤòÆþ¤ì¤¿¡£
¤³¤ÎPORTA¤ÈPORTB¤ËÂФ·¤Æ¥Æ¥¹¥È¥Ù¥ó¥Á¤«¤éÇÈ·Á¤òÆþÎϤ¹¤ë¡£

linedelay_c

 



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library IEEE;
use IEEE.std_logic_1164.all;

entity TEST is
end TEST;

architecture BEHAVIOR of TEST is

    component LINEDELAY
        generic
        (
            linedelay       : time
        );
        port
        (
            PORTA           : inout std_logic;
            PORTB           : inout std_logic
        );
    end component;

    signal  PORTA   : std_logic;
    signal  PORTB   : std_logic;
    signal  PORTA_S : std_logic;
    signal  PORTB_S : std_logic;

begin

    C_LINEDELAY : LINEDELAY
    generic map
    (
        linedelay       => 10 ns
    )
    port map
    (
        PORTA           => PORTA_S,
        PORTB           => PORTB_S
    );

    process begin
        PORTA <= 'Z';
        PORTB <= 'Z';
        wait for 100 ns;
        PORTA <= '1';
        wait for 100 ns;
        PORTA <= '0';
        wait for 100 ns;
        PORTA <= 'Z';
        PORTB <= '1';
        wait for 100 ns;
        PORTB <= '0';
        wait for 100 ns;
        PORTB <= 'Z';
        wait for 100 ns;
        PORTA <= '1';
        PORTB <= '0';
        wait for 100 ns;
        PORTA <= '0';
        PORTB <= '1';
        wait for 100 ns;
        PORTA <= '1';
        wait for 100 ns;
        PORTA <= '0';
        PORTB <= '0';
        wait for 100 ns;
    end process;

    PORTA_S <= PORTA;
    PORTB_S <= PORTB;

end BEHAVIOR;


¤½¤·¤ÆÆ°ºî·ë²Ì¤ÎÇÈ·Á¤Ï¤³¤ó¤Ê´¶¤¸¡£

linedelay_w

 

PORTA¤«¤é½ÐÎϤ·¤¿Ãͤϡ¢¤¹¤°¤ËPORTA_S¤ËÈ¿±Ç¤µ¤ì¤ë¤¬PORTB_S¤Ë¤ÏÃٱ䤬Æþ¤Ã¤Æ¤¤¤ë»ö¤¬Ê¬¤«¤ë¡£
µÕ¤ËPORTB¤«¤é½ÐÎϤ·¤¿Ãͤϡ¢¤¹¤°¤ËPORTB_S¤ËÈ¿±Ç¤µ¤ì¤ë¤¬PORTA_S¤Ë¤ÏÃٱ䤬Æþ¤Ã¤Æ¤¤¤ë¡£
¤Þ¤¿¡¢Æ±»þ¤ËPORTA_S¤ÈPORTB_S¤ÎÃͤòÊѲ½¤µ¤»¤Æ¤âÃÙ±ä»þ´Öʬ¤Î¥·¥ç¡¼¥È¤¬'X'¤ÇºÆ¸½¤µ¤ì¤Æ¤¤¤ë¡£

¼¡¤Ë´Î¿´¤Ê¥â¥Ç¥ë¤Î¥½¡¼¥¹¤¬¤³¤ì¡£


library IEEE;
use IEEE.std_logic_1164.all;

entity LINEDELAY is
    generic
    (
        linedelay       : time
    );
    port
    (
        PORTA           : inout std_logic;
        PORTB           : inout std_logic
    );
end LINEDELAY;

architecture BEHAVIOR of LINEDELAY is

    signal  PORTA_X     : std_logic;
    signal  PORTB_X     : std_logic;

begin

    PROCESS
        VARIABLE last_time : time;
        VARIABLE transact : boolean;
    BEGIN
            WAIT ON PORTA'TRANSACTION, PORTB_X UNTIL (last_time /= NOW or PORTB_X'EVENT);

            if ( PORTA'TRANSACTION'EVENT ) then
                PORTA <= 'Z';
                transact := TRUE;
                last_time := NOW;
            else
                transact := FALSE;
            end if;

            WAIT FOR 0 ns;

            if ( transact = TRUE ) then
                PORTA_X <= transport PORTA after linedelay;
            end if;
            PORTA <= PORTB_X;

    END PROCESS;

    PROCESS
        VARIABLE last_time : time;
        VARIABLE transact : boolean;
    BEGIN
            WAIT ON PORTB'TRANSACTION, PORTA_X UNTIL (last_time /= NOW or PORTA_X'EVENT);

            if ( PORTB'TRANSACTION'EVENT ) then
                PORTB <= 'Z';
                last_time := NOW;
                transact := TRUE;
            else
                transact := FALSE;
            end if;

            WAIT FOR 0 ns;

            if ( transact = TRUE ) then
                PORTB_X <= transport PORTB after linedelay;
            end if;
            PORTB <= PORTA_X;

    END PROCESS;

end BEHAVIOR;


PORTA_X¤ÈPORTB_X¤Ë¡¢¤½¤ì¤¾¤ì¤ÎÁÐÊý¸þ¥Ý¡¼¥È¤ÎÃͤò¥³¥Ô¡¼¤·¡¢¤½¤ì¤òÃٱ䤵¤»¤ÆÈ¿ÂЦ¤Î¥Ý¡¼¥È¤ËÂåÆþ¤·¤Æ¤¤¤ë¡£
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¤Þ¤¿¡¢ÊѤʡÖWAITʸ¡×¡¢¤³¤ì¤ÏÁÐÊý¸þ¥Ý¡¼¥È¤Î¥È¥é¥ó¥¶¥¯¥·¥ç¥ó¤Ï»þ´Öñ°Ì¤¢¤¿¤ê£±ÅÙ¤·¤«Æ°ºî¤µ¤»¤¿¤¯Ìµ¤¤¤Î¤ËÂФ·È¿ÂЦ¤ÎÁÐÊý¸þ¥Ý¡¼¥È¤ò¥³¥Ô¡¼¤·¤¿ÃͤΥ¤¥Ù¥ó¥È¤Ï²¿²ó¤Ç¤âưºî¤µ¤»¤ë¤¿¤á¤Î¾ò·ï¤À¡£
ÁÐÊý¸þ¥Ý¡¼¥È¤Î¥È¥é¥ó¥¶¥¯¥·¥ç¥ó¤ò»þ´Öñ°Ì¤¢¤¿¤ê£±ÅÙ¤·¤«Æ°ºî¤µ¤»¤¿¤¯¤Ê¤¤Íýͳ¤Ï¡¢¼«Ê¬¤Ç¥È¥é¥ó¥¶¥¯¥·¥ç¥ó¤òȯÀ¸¤µ¤»¤Æ¤¤¤ë¤¿¤á¤³¤Î¾ò·ï¤¬Ìµ¤¤¤È¥ë¡¼¥×¤Ë´Ù¤Ã¤Æ¤·¤Þ¤¦¤«¤é¤Ç¤¢¤ë¡£
¤¿¤À¡¢ÁÐÊý¸þ¥Ý¡¼¥È¤Î°ìÈֺǽé¤Î¥È¥é¥ó¥¶¥¯¥·¥ç¥ó¤Çưºî¤µ¤»¤Æ¤¤¤ë¤¿¤á¡¢¥È¥é¥ó¥¶¥¯¥·¥ç¥ó¤¬È¯À¸¤·¤¿¥Ç¥ë¥¿»þ´Ö¤Î¸å¤Î¥Ç¥ë¥¿»þ´Ö¤ËÃͤ¬ÊѲ½¤¹¤ë¤è¤¦¤Ê¿®¹æ¤Ç¤Ï¤¦¤Þ¤¯Æ°ºî¤·¤Ê¤¤¡£
¾°¡¢°ÊÁ°¾Ò²ð¤·¤¿VHDL TIPS ¡Ö¥¢¥Ê¥í¥°¥¹¥¤¥Ã¥Á¤Î¥â¥Ç¥ê¥ó¥°¡×¤â¤½¤¦¤À¤¬¡¢¤³¤Î¼ê¤Î¼êË¡¤Ï¤³¤ÎÀ©¸Â¤¬¤Ä¤­¤Þ¤È¤Ã¤Æ¤·¤Þ¤¦¡£



Åê¹Æ»þ¹ï(21:44)¨¢¥³¥á¥ó¥È(3)¨¢VHDL 

2007ǯ09·î21Æü

VHDL TIPS ¡Ö°À­"DRIVING_VALUE"¤Î»ÈÍÑË¡¡×

£Ö£È£Ä£Ì¤Ç¤Ï½ÐÎϥݡ¼¥È¤Ë³ä¤êÅö¤Æ¤¿ÃͤòÆâÉô¤Ç»²¾È¤¹¤ë»ö¤Ï½ÐÍè¤Ê¤¤¡£
½ê¤¬¡¢£Ö£È£Ä£Ì£¹£³¤Ç¥³¥ì¤ò²Äǽ¤Ë¤¹¤ë¥¢¥È¥ê¥Ó¥å¡¼¥È¡ÖDRIVING_VALUE¡×¤¬Äɲ䵤줿¡£

°Ê²¼¤Ë»ÈÍÑÎã¤ò¾Ò²ð¤¹¤ë¡£


library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_signed.all;

entity COUNT is
    port
    (
        CLK     : in    std_logic;
        COUNT   : out   std_logic_vector(7 downto 0) := (others => '0')
    );
end COUNT;

architecture rtl of COUNT is

begin

    process ( CLK ) begin
        if ( CLK'event and CLK = '1' ) then
            COUNT <= COUNT'DRIVING_VALUE + '1';        -- ÆâÉô»²¾È
        end if;
    end process;

end rtl;


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package shared_pkg is
    shared variable SH_INT      : integer;
end shared_pkg;

 

library IEEE;
use IEEE.std_logic_1164.all;

library work;
use work.shared_pkg.all;

entity a is
    port
    (
        CLK             : in    std_logic;
        DATA           : out   integer
    );
end a;

architecture a of a is
    component b
        port
        (
            CLK             : in    std_logic
        );
    end component;
begin
    u_b : b port map( CLK );
    process ( CLK ) begin
        if ( CLK'event and CLK = '1' ) then
            DATA <= SH_INT;
        end if;
    end process;
end a;

 

library IEEE;
use IEEE.std_logic_1164.all;

library work;
use work.shared_pkg.all;

entity b is
    port
    (
        CLK             : in    std_logic
    );
end b;

architecture b of b is
begin
    process ( CLK ) begin
        if ( CLK'event and CLK = '1' ) then
            SH_INT := SH_INT + 1;
        end if;
    end process;
end b;


¤³¤ÎÎã¤Ç¤Ï¡¢£²¤Ä¤Î¥¢¡¼¥­¥Æ¥¯¥Á¥ã¤«¤é¥Ñ¥Ã¥±¡¼¥¸¤ÇÀë¸À¤·¤¿¶¦Í­ÊÑ¿ô¤Ë¥¢¥¯¥»¥¹¤·¤Æ¤¤¤ë¡£

¼¡¤Ë¡¢£Ö£È£Ä£Ì£²£°£°£²¤ÎÎã
package shared_pkg is     -- ¥×¥í¥Æ¥¯¥È¥Ç¡¼¥¿¥¿¥¤¥×
    type SH_TEST is protected
        -- ½ñ¤­¹þ¤ß´Ø¿ô
        procedure write ( data : in integer );
        -- ÆÉ¤ß½Ð¤·´Ø¿ô
        impure function read return integer;
    end protected SH_TEST;

    -- ¶¦Í­ÊÑ¿ô¤ò¥×¥í¥Æ¥¯¥È¥¿¥¤¥×¤ÇÀë¸À
    shared variable SH_INT      : SH_TEST;

end shared_pkg;

package body shared_pkg is

    type SH_TEST is protected body
        -- ¼Â¥Ç¡¼¥¿
        variable buf : integer := 0;
        -- ½ñ¤­¹þ¤ß´Ø¿ô
        procedure write ( data : in integer ) is
        begin
            buf := data;
        end;
        -- ÆÉ¤ß½Ð¤·´Ø¿ô
        impure function read return integer is
        begin
            return buf;
        end;
    end protected body SH_TEST;

end shared_pkg;

 

library IEEE;
use IEEE.std_logic_1164.all;

library work;
use work.shared_pkg.all;

entity a is
    port
    (
        CLK             : in    std_logic;
        DATA            : out   integer
    );
end a;

architecture a of a is
    component b
        port
        (
            CLK             : in    std_logic
        );
    end component;
begin
    process ( CLK ) begin
        if ( CLK'event and CLK = '1' ) then
            DATA <= SH_INT.read;
        end if;
    end process;
    u_b : b port map( CLK );
end a;

 

library IEEE;
use IEEE.std_logic_1164.all;

library work;
use work.shared_pkg.all;

entity b is
    port
    (
        CLK             : in    std_logic
    );
end b;

architecture b of b is
begin
    process ( CLK ) begin
        if ( CLK'event and CLK = '1' ) then
            SH_INT.write( SH_INT.read + 1 );
        end if;
    end process;
end b;


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library IEEE;
use IEEE.std_logic_1164.all;

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library work;
use work.ver_get.all;

entity top is
    generic
    (
        -- ¥·¥ß¥å¥ì¡¼¥·¥ç¥ó¤ò¹Ô¤¦¾ì¹ç¤Ï¡¢
        -- ¥Æ¥¹¥È¥Ù¥ó¥Á¤«¤é¡ÖSIM_MODE¡×¤ò1¤Ë¤·¤Æ¸Æ¤Ó½Ð¤¹¡£
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        SIM_MODE            : integer := 0
    );
    port
    (
        VER_OUT         : out   std_logic_vector(31 downto 0)
    );
end top;

architecture top of top is

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    constant    VERSION : std_logic_vector(31 downto 0)
                                := get_version( SIM_MODE, "ver.txt" );

begin

    VER_OUT <= VERSION;

end top;


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